The BLIF Code Generator (-tblif)
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The BLIF code generator supports emitting the design to a blif format
file as accepted by:
ABC: A System for Sequential Synthesis and Verification
This package contains tools sometimes used by ASIC designers. This
blif target emits .blif file that the ABC system can read int via
the "read_blif" command.
USAGE
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This code generator is intended to process structural Verilog source
code. To convert a design to blif, use this command::
% iverilog -tblif -o.blif